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Source: http://www.ps3devwiki.com/index.php?title=Syscon_Hardware
Contents |
General Information
Syscon is the main power controller chip. It is responsible for powering up the various power systems and for configuring and initialising the CELL, RSX and southbridge. It communicates with these devices via seperate SPI busses. There is external access by JTAG (Which appears to have been disabled after factory programming) and Serial.
Generation 1
Packaging
The first generation of the chip comes in a 200 pin BGA package as per below:
T R P N M L K J H G F E D C B A 1 . . . . . . . . . . . . . . . . 1 2 . . . . . . . . . . . . . . . . 2 3 . . . . 3 4 . . . . . . . . . . . . . . 4 5 . . . . . . . . . . . . . . 5 6 . . . . . . . . . . . . . . 6 7 . . . . . . . . . . . . . . 7 8 . . . . . . . . . . . . 8 9 . . . . . . . . . . . . 9 10 . . . . . . . . . . . . . . 10 11 . . . . . . . . . . . . . . 11 12 . . . . . . . . . . . . . . 12 13 . . . . . . . . . . . . . . 13 14 . . . . 14 15 . . . . . . . . . . . . . . . . 15 16 . . . . . . . . . . . . . . . . 16 T R P N M L K J H G F E D C B A
Pinout
Work in progress
| Pin # | Name | Port | Description |
|---|---|---|---|
| T2 | /BE_INT | Port M Cell Control Line | |
| R1 | PM7 | ||
| R2 | PM6 | ||
| P1 | BE_POWGOOD | ||
| P2 | /BE_RESET | ||
| N1 | BE_SPI_CLK | Cell SPI Bus | |
| N2 | BE_SPI_DO | ||
| M1 | BE_SPI_DI | ||
| M2 | /BE_SPI_CS | ||
| L4 | PL8 | Port N | unused |
| L5 | PL7 | ||
| K4 | PL6 | ||
| K5 | PL5 | ||
| J4 | PL4 | ||
| J5 | PL3 | ||
| H4 | PL2 | ||
| H5 | PL1 | ||
| H6 | PL0 | ||
| A8 | SB_SPI_CLK | Port K | Southbridge SPI Bus |
| B8 | SB_SPI_DO | ||
| A9 | SB_SPI_DI | ||
| B9 | /SB_SPI_CS | ||
| A10 | SEL2_I2C_SCL | ||
| B10 | SEL2_I2C_SDA | ||
| A11 | ACDC_STBY | ||
| B11 | PK0 | ||
| B5 | PJ7 | Port J | |
| A5 | DISC_OUT12_SW | ||
| B2 | DISC_OUT8_SW | ||
| A2 | DISC_IN | ||
| B3 | SW_10 | ||
| A3 | SW_0 | ||
| B4 | SW_8_B | ||
| A4 | SW_8_C | ||
| L16 | SW_PCI | Port I | |
| L15 | DISC_CHUCK | ||
| M16 | DISC_PHOT_LED | ||
| M15 | SW_2 | ||
| N16 | DIAG_MODE | ||
| N15 | BACKUP_MODE | ||
| E6 | /HDMI_INT | Port H | |
| D6 | VD_CECI0 | ||
| E7 | PH5 | ||
| D7 | /RS_POW_FAIL | ||
| E8 | /MUL_CHKSTP_IN | ||
| D8 | /MUL_TRG_IN | ||
| E9 | /SYS_THR_ALRT | ||
| D9 | /SB_INT | ||
| M11 | SW_ATA | Port G | |
| N11 | SW_4_A | ||
| M10 | /XDR_FET_VREF | ||
| N10 | /XDR_FET_SCK | ||
| M9 | BUZZER | ||
| N9 | SW_PWM | ||
| M8 | FANPWM1 | ||
| N8 | FANPWM0 | ||
| E10 | /MUL_CHKSTP_OUT | Port F | |
| D10 | /MUL_TAG_OUT | ||
| E11 | /SB_CGRESET | ||
| D11 | /SB_RESET | ||
| E12 | BT_WAKEON | ||
| D12 | BE_VCS_1.25_ON | ||
| E13 | BE_VCS_1.30_ON | ||
| D13 | SW_1A | ||
| A12 | /EJECT_SW | Port E | |
| B12 | /POW_SW | ||
| A13 | /SB_EBUS_RESET | ||
| B13 | SB_EBUS_BRDY | ||
| A14 | PE3 | ||
| B14 | VD_CECI1 | ||
| A15 | /BE_POW_FAIL | ||
| B15 | /POW_FAIL | ||
| F13 | SW_5_B | Port D | |
| F12 | MK_EN | ||
| G13 | BEVRM_VID5 | ||
| G12 | BEVRM_VID4 | ||
| H13 | BEVRM_VID3 | ||
| H12 | BEVRM_VID2 | ||
| J13 | BEVRM_VID1 | ||
| J12 | BEVRM_VID0 | ||
| K13 | SW_HDD | Port C | |
| K12 | I2CBUS_EN | ||
| L13 | RSXVRM_VID5 | ||
| L12 | RSXVRM_VID4 | ||
| M13 | RSXVRM_VID3 | ||
| M12 | RSXVRM_VID2 | ||
| N13 | RSXVRM_VID1 | ||
| N12 | RSXVRM_VID0 | ||
| T15 | SW_8_A | Port B | |
| R14 | SW_7_A | ||
| T14 | SW_6 | ||
| R13 | SW_1_B | ||
| T13 | SW_4_B | ||
| R12 | SW_3 | ||
| T12 | VD_CECO1 | ||
| R11 | VD_CECO0 |
Generation 2
thumb|Syscon 2nd Generation (QFP Packaging)
QFP Package : 128 pins
Currently there is no known pin labelling for this generation
CECHG02 Pinout
Topside Pinout
| Pin # | Name | Description |
|---|---|---|
| B3 | SW_10 | Unknown |
| A6 | MC_RESERVED2 | Unknown |
| E10 | MUL_CHKSTP_OUT | Unknown |
| C15 | VSS | Power Ground |
| B16 | OSCOUT | Goes to unpopulated crystal |
| C16 | OSCIN | From unpupulated crystal |
| B15 | POW_FAIL | Power Failure Signal |
| H1 | PN5 | Unknown |
| H2 | PN6 | Unknown |
| R1 | PM7 | Unknown |
| R2 | PM6 | Unknown |
| M4 | SW9 | Unknown |
| M10 | XDR_FET_SCK | Unknown |
Bottomside Pinout
thumbnail|Syscon Bottom Pinouts
| Pin # | Name | Description |
|---|---|---|
| R5 | VDD | +3.3v |
| R7 | DVDD | +1.8v |
| C15 | VSS | Power Ground |
| N16 | DIAG_MODE | Unknown |
| N15 | BACKUP_MODE | Unknown |
| P16 | UART0_TxD | Serial |
| P15 | UART0_RxD | Serial |
| R9 | PQ1 | Unknown |
| B12 | POW_SW | Power Switch |
| A12 | EJECT_SW | Eject Switch |
| L7 | JNTAST | JTAG |
| L8 | JRTCK | JTAG |
| L9 | JTMS | JTAG |
| K7 | JTDI | JTAG |
| K8 | JTCK | JTAG |
| K9 | JTDO | JTAG |
| M6 | SW_7_B | Unknown |
| M8 | FANPWM1 | Unknown |
| E5 | GX_VSRT | Unknown |
| B5 | DVE_RST | Unknown |
| G4 | HDMI_RST1 | Unknown |
| D4 | XDR_FET_RST | Unknown |