PcParallelPortExplained

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Traditionally IBM PC systems have allocated their first two parallel ports according to the configuration in the table below.

PORT NAME Interrupt Starting I/O Ending I/O
LPT1 IRQ 7 0x378 0x37f
LPT2 IRQ 5 0x278 0x27f

Contents

Background

The first PC-compatible parallel printer ports were unidirectional, allowing 8-bit data transfer only from the host to the peripheral. These early Standard Printer Ports (SPP) implemented eight data lines and used nine handshaking lines, four output from the host and five input to the host. Later came the PS/2 type bi-directional parallel port (BPP); this bi-directional port simply added the capability to read 8-bit data from the peripheral to the host. Both the SPP and BPP type implemented three registers for the control and monitoring of the data and handshaking lines; these are the data port, status port, and control port. The SPP type parallel ports are most commonly used for printers, plotters, keys, etc.

The IEEE 1284 standard, "Standard Signaling Method for a Bi-directional Parallel Peripheral Interface for Personal Computers", sought to correct the major drawbacks to the original parallel port structure. The first major obstacle was that not all parallel peripherals used the same mechanical interface, and thus the maximum cable distance between computer and peripheral could only extend 6 feet. IEEE 1284 sets standards for the cable, connector, and electrical interface, which guarantee interoperability between all parallel peripherals. The specified configuration ensures that data integrity is maintained, even at the highest data rates, and at a distance of up to 30 feet.

Two new types of parallel ports with extended features are now available: the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP). EPP and ECP are standards defined by IEEE 1284 and Microsoft ECP Specifications. Both EPP and ECP ports may be operated in the SPP and bi-directional modes; however, operation in their feature modes requires both compatible peripherals and appropriate software drivers. This paper is intended to explain just some of the major differences of the ECP and EPP modes.

Generally, EPP is used primarily by non-printer peripherals, CD ROM, tape drive, hard drive, network adapters, etc., while ECP is aimed at newer generation of printers and scanners. Currently, new products have been released having support for a mixture of these protocols.

The Similarities

Parallel data transfer was largely performed by software in SPP and BPP systems, and thus data transfer rates were limited to 150 KBps in the forward direction (compatibility or "Centronics" mode) and 50 KBps in the reverse direction (nibble and byte modes). In SPP and BPP systems, data is placed on the port's data lines, the printer status is checked for no errors and that it is not busy, then a data strobe is generated by the software to clock the data to the printer. Compatibility or "Centronics" mode requires four I/O instructions and at least as many additional instructions just to output one byte. Nibble mode is the most software intensive with ten I/O instructions to clock in one byte of data while byte mode requires only five I/O instructions. Both modes operations does not have much visible effect on peripherals that have low reverse channel requirements, such as printers, but can be nearly intolerable when used for LAN adapters, disk drives, or CD ROM drives.

The EPP and ECP modes are the two high speed data transfer protocols of the IEEE 1284 standard. Both EPP and ECP standards specify a hardware driven handshake system of data transfer which allows significantly higher data transfer speeds of up to 2 MBps in ISA systems. In these modes, data transfer takes place as a single software instruction, and the rest of the transfer is handled by hardware. This allows an EPP/ECP port to function as a 16- or 32-bit data transfer interface using 8-bit I/O hardware, in effect enabling EPP/ECP capable peripherals to achieve the same speed and efficiency as their ISA bus counterparts.

The Differences

An EPP parallel port implements two registers in addition to the standard data, status, and control ports. An EPP data port and an EPP address port allow EPP data transfers. However, the entire data transfer still occurs within one ISA I/O cycle. Tri-stateable outputs allow the EPP port to be used as a data bus for multiple EPP compatible devices. On a "read-from" or "write-to" any EPP port, automatic handshaking is performed and the host bus cycle is extended until the transfer is complete. A watchdog timer prevents any system lockup, which may occur in a failed transfer cycle. Normally an indirect addressing location in the peripheral and a subsequent read or write of the EPP data port transferring data to the specified address.

An ECP parallel port features two modes, namely data and command cycles, which can greatly enhance data transfer rates. In the Parallel Port Data FIFO Mode, data written or DMAed to a 16-byte FIFO is automatically transferred to a peripheral using standard parallel port protocol. The ECP Parallel Port Mode allows bi-directional data transfer using automatic interlocked handshaking via the ECP protocol. In addition to DMA support and 16-byte FIFOs, the ECP parallel port's advantages include run length encoded (RLE) decompression, channel addressing, and peer-to-peer capability.

Unlike EPP, when the ECP protocol was proposed, a standard register implementation was also proposed through Microsoft ECP Specification. This document defines features that are implementation specific, which the IEEE 1284 standard could not address. These features include the RLE compression, the 16-byte FIFOs, and DMA as well as programmed I/O for the host register interface.

The RLE feature enables real time data compression that can achieve compression ratios up to 64:1. This is particularly useful for printers and scanners that are transferring large raster images that have large strings of identical data. In order for the RLE mode to be enabled both the host and the peripheral must support it.

Channel addressing is, conceptually, a little different than the EPP addressing. Channel addressing is intended to be used to address multiple logical devices within a single physical device. Think of this in terms of a new multi-function device such as FAX/Printer/Modem. Within one physical package, having a single parallel port attached, there is a printer, fax and modem. Each of these separate functions can be thought of as separate logical devices within the same package. Using the ECP channel addressing to access each of these devices, you could receive data from the modem data device while the printer data channel is busy processing a print image. With the compatibility mode protocol, if the printer gets busy then no more communication can occur until the printer data channel if free. With ECP, the software driver simply addresses another channel and communication can continue.

There is another difference between the ECP and EPP protocols. With EPP, the software driver may intermix read and write operations without any overhead or protocol handshaking. With the ECP protocol, changes in the data direction must be negotiated. The host must request a reverse channel transfer by asserting nReverseRequest and then wait for the peripheral to acknowledge the request by asserting nAckReverse. Only then can a reverse channel data transfer take place. In addition, since the previous transfer may have been DMA driven, the host software must either wait for the DMA to complete, or interrupt the DMA, backflush the FIFO to determine the exact transferred byte count, and then request the reverse channel. This adds a fair amount of overhead with peripherals that require a lot of intermixed reading and writing of registers or small buffers.

In The End...

Although, there are some keen differences between ECP and EPP, both essentially support the higher throughput of today's variety of devices via the parallel ports. The major difference is that the PCI series cards do not support ECP. As mentioned above, ECP protocol is meant to be driven by DMA rather than explicit I/O operations, and the PCI bus does not support DMA transfers.

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